When in operation, CPUs of microprocessors, such as general purpose microprocessors, microcontrollers, digital signal processors or other types of microprocessors, perform a certain task, such as the execution of a series of instructions defined by, for example, a computer program. Other devices or computer programs can have the CPU perform requested services by generating interrupt requests. An interrupt request may for example be transmitted by a peripheral device of the microprocessor to the CPU. The interrupt request may for example be sent by an external memory device (external to the microprocessor), such as a hard-disk, to signal the completion of task, such as a data transfer from or to the peripheral. Also, the interrupt request may for example be used to transmit information to the CPU. For instance, a system timer may periodically transmit interrupt requests which can be used by the CPU to establish a time-base.
The interrupt requests are propagated to an interrupt controller via multiple interrupt request lines. Once the interrupt controller identifies an active interrupt request line, it may grant the interrupt request and forward the interrupt request to the CPU. In response to the interrupt request, the CPU will interrupt the task being performed and perform a sequence of steps, generally referred to as an interrupt handler or interrupt service routine, associated with the requested interrupt. After handling the interrupt, the CPU returns (in normal operations) to the previous interrupted task.
However, in case a CPU becomes unavailable, the handling of the interrupts and of the processing tasks associated to the corresponding interrupts cannot be guaranteed anymore. For example, in applications where safety may be valued, such as automotive applications, there is a need to provide fail safe or fail-operational systems. In typical microcontroller or microprocessor units used in such applications, a CPU of the microcontroller or microprocessor unit is shut down or halted when the CPU becomes unavailable (e.g. to reduce power consumption in the microcontroller or when a fault is detected in the CPU of the microprocessor). When the CPU is shut down or halted, the tasks handled by the processing unit are suspended, together with the processing tasks associated with the interrupts handling.
Gountanis, R. J.; Viss, N. L., “A method of processor selection for Interrupt handling in a multiprocessor system” Proceeding of the IEEE, vol. 54, no. 12, pp. 1812-1819, December 1966 discloses a method of assigning external interrupts to CPUs in a multiprocessor system. A hardware component called Interrupt Directory selects a most appropriate CPU in the multiprocessor system according to an Interrupt Priority (IP) number associated with each possible external interrupt condition and an Interruptibility Index (II) assigned to each task in every CPU of the multiprocessor system. If the Interrupt priority is greater than the Interruptibility Index, then the external interrupt is routed to a CPU executing a task with the corresponding Interruptibility Index.
A disadvantage of the disclosed multiprocessor system described in this document is that only the processing tasks signalled with interrupts with high priority are assigned in the multi-processor system based on a comparison between the Interrupt Priority (IP) and the Interruptibility Index (II). Furthermore, although the disclosed multiprocessor system redistributes the load between the CPUs in the multiprocessor systems, it lacks safety functionality, as desirable in for example, in fail-operational systems.